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400 msps, 14-bit, 1.8 v cmos direct digital synthesizer ad9953 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2004C2009 analog devices, inc. all rights reserved. features 400 msps internal clock speed integrated 14-bit dac 32-bit tuning word phase noise C120 dbc/hz @ 1 khz offset (dac output) excellent dynamic performance >80 db sfdr @ 160 mhz (100 khz offset) a out serial i/o control 1.8 v power supply software and hardware controlled power-down 48-lead tqfp/ep package support for 5 v input levels on most digital inputs pll refclk multiplier (4 to 20) internal oscillator, can be driven by a single crystal phase modulation capability multichip synchronization applications agile vhf/uhf lo frequency synthesis fm chirp source for radar and scanning systems nonlinear-shaped psk/fsk modulator test and measurement equipment functional block diagram 1024 32 static ram cos(x) control registers oscillator/buffer sync enable i/o update z ?1 osk pwrdwnctl refclk refclk crystal out i/o port ps<1:0> ram data <31:18> frequency tuning word ram data dds clock dds clock phase accumulator reset mux system clock system clock dac_r set dds core phase offset phase accumulator z ?1 iout iout ram data dac sync_in phase offset word sync_clk reset timing and control logic 4 ?20 clock multiplier 4 ad9953 32 14 14 14 32 r a m a d d r e s s 10 ram control 3 19 14 0 m u x 32 m u x m u x 03357-0-001 figure 1.
ad9953 rev. a | page 2 of 32 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? revision history ............................................................................... 2 ? general description ......................................................................... 3 ? electrical specifications ................................................................... 4 ? absolute maximum ratings ............................................................ 6 ? esd caution .................................................................................. 6 ? pin configuration ............................................................................. 7 ? pin function descriptions .............................................................. 8 ? typical performance characteristics ............................................. 9 ? theory of operation ...................................................................... 12 ? component blocks ..................................................................... 12 ? modes of operation ................................................................... 19 ? programming ad9953 features .............................................. 22 ? serial port operation ................................................................. 25 ? instruction byte .......................................................................... 27 ? serial interface port pin description ....................................... 27 ? msb/lsb transfers .................................................................... 27 ? suggested application circuits ..................................................... 29 ? outline dimensions ....................................................................... 30 ? ordering guide .......................................................................... 30 ? revision history 5/09rev. 0 to rev. a changes to absolute maximum ratings section ......................... 6 changes to table 3 ............................................................................ 8 changes to table 5 .......................................................................... 14 changes to figure 22 ...................................................................... 25 changes to serial port operation section ................................... 25 changes to serial interface port pin description section ........ 27 changes to figure 29 ...................................................................... 29 updated outline dimensions ....................................................... 30 changes to ordering guide .......................................................... 30 1/04revision 0: initial version
ad9953 rev. a | page 3 of 32 general description the ad9953 is a direct digital synthesizer (dds) featuring a 14-bit dac operating up to 400 msps. the ad9953 uses advanced dds technology, coupled with an internal high speed, high performance dac to form a digitally programmable, complete high frequency synthesizer capable of generating a frequency-agile analog output sinusoidal waveform at up to 200 mhz. the ad9953 includes an integrated 1024 32 static ram to support flexible frequency sweep capability in several modes. the ad9953 is designed to provide fast frequency hopping and fine tuning resolution (32-bit frequency tuning word). the frequency tuning and control words are loaded into the ad9953 via a serial i/o port. the ad9953 is specified to operate over the extended industrial temperature range of C40c to +105c.
ad9953 rev. a | page 4 of 32 electrical specifications table 1. unless otherwise noted, avdd, dvdd = 1.8 v 5%, dvdd_i/o = 3.3 v 5%, r set = 3.92 k, external reference clock frequency = 20 mhz with refclk multiplier enabled at 20 . dac output must be referenced to avdd, not agnd. parameter temp min typ max unit ref clock input characteristics frequency range refclk multiplier disabled full 1 400 mhz refclk multiplier enabled at 4 full 20 100 mhz refclk multiplier enabled at 20 full 4 20 mhz input capacitance 25c 3 pf input impedance 25c 1.5 k duty cycle 25c 50 % duty cycle with refclk multiplier enabled 25c 35 65 % refclk input power 1 full C15 0 +3 dbm dac output characteristics resolution 14 bits full-scale output current 25c 5 10 15 ma gain error 25c C10 +10 %fs output offset 25c 0.6 a differential nonlinearity 25c 1 lsb integral nonlinearity 25c 2 lsb output capacitance 25c 5 pf residual phase noise @ 1 khz offset, 40 mhz a out refclk multiplier enabled @ 20 25c C105 dbc/hz refclk multiplier enabled @ 4 25c C115 dbc/hz refclk multiplier disabled 25c C132 dbc/hz voltage compliance range 25c avdd C 0.5 avdd + 0.5 v wideband sfdr 1 mhz to 10 mhz analog out 25c 73 dbc 10 mhz to 40 mhz analog out 25c 67 dbc 40 mhz to 80 mhz analog out 25c 62 dbc 80 mhz to 120 mhz analog out 25c 58 dbc 120 mhz to 160 mhz analog out 25c 52 dbc narrow-band sfdr 40 mhz analog out (1 mhz) 25c 87 dbc 40 mhz analog out (250 khz) 25c 89 dbc 40 mhz analog out (50 khz) 25c 91 dbc 40 mhz analog out (10 khz) 25c 93 dbc 80 mhz analog out (1 mhz) 25c 85 dbc 80 mhz analog out (250 khz) 25c 87 dbc 80 mhz analog out (50 khz) 25c 89 dbc 80 mhz analog out (10 khz) 25c 91 dbc 120 mhz analog out (1 mhz) 25c 83 dbc 120 mhz analog out (250 khz) 25c 85 dbc 120 mhz analog out (50 khz) 25c 87 dbc 120 mhz analog out (10 khz) 25c 89 dbc 160 mhz analog out (1 mhz) 25c 81 dbc 160 mhz analog out (250 khz) 25c 83 dbc 160 mhz analog out (50 khz) 25c 85 dbc 160 mhz analog out (10 khz) 25c 87 dbc
ad9953 rev. a | page 5 of 32 parameter temp min typ max unit timing characteristics serial control bus maximum frequency full 25 mbps minimum clock pulse width low full 7 ns minimum clock pulse width high full 7 ns maximum clock rise/fall time full 2 ns minimum data setup time dvdd_i/o = 3.3 v full 3 ns minimum data setup time dvdd_i/o = 1.8 v full 5 ns minimum data hold time full 0 ns maximum data valid time full 25 ns wake-up time 2 full 1 ms minimum reset pulse width high full 5 sysclk cycles 3 i/o update (ps0/ps1) to sync_clk setup time dvdd_i/o = 3.3 v full 4 ns i/o update (ps0/ps1) to sync_clk setup time dvdd_i/o = 1.8 v full 6 ns i/o update (ps0/ps1), sync_clk hold time full 0 ns latency i/o update (ps0/ps1) to frequency change prop delay 25c 24 sysclk cycles i/o update (ps0/ps1) to phase offset change prop delay 25c 24 sysclk cycles i/o update (ps0/ps1) to amplitude change prop delay 25c 16 sysclk cycles cmos logic inputs logic 1 voltage @ dvdd_i/o (pin 43) = 1.8 v 25c 1.25 v logic 0 voltage @ dvdd_i/o (pin 43) = 1.8 v 25c 0.6 v logic 1 voltage @ dvdd_i/o (pin 43) = 3.3 v 25c 2.2 v logic 0 voltage @ dvdd_i/o (pin 43) = 3.3 v 25c 0.8 v logic 1 current 25c 3 12 a logic 0 current 25c 12 a input capacitance 25c 2 pf cmos logic outputs (1 ma load) dvdd_i/o = 1.8 v logic 1 voltage 25c 1.35 v logic 0 voltage 25c 0.4 v cmos logic outputs (1 ma load) dvdd_i/o = 3.3 v logic 1 voltage 25c 2.8 v logic 0 voltage 25c 0.4 v power consumption (avdd = dvdd = 1.8 v) single-tone mode 25c 162 171 mw rapid power-down mode 25c 150 160 mw full-sleep mode 25c 20 27 mw synchronization function 4 maximum sync clock rate (dvdd_i/o = 1.8 v) 25c 62.5 mhz maximum sync clock rate (dvdd_i/o = 3.3 v) 25c 100 mhz sync_clk alignment resolution 5 25c 1 sysclk cycles 1 to achieve the best possible phase noise, the largest amplitude clock possible should be used. reducing the clock input amplit ude will reduce the phase noise performance of the device. 2 wake-up time refers to the recovery from analog power-do wn modes (see the power-down functions of the ad9953 section). the longest time requir ed is for the reference clock multiplier pll to relock to the reference. the wake-up time assumes there is no capacitor on dacbp and that the recommended pll loop filter values are used. 3 sysclk cycle refers to the actual clock frequency used on-chip by the dds. if the reference clock multiplier is used to multip ly the external reference clock frequency, the sysclk frequency is the external frequency multiplied by the reference clock multiplication factor. if the reference clock multiplier is not used, the sysclk frequency is the same as the external reference clock frequency. 4 sync_clk = ? sysclk rate. for sync_clk rates 50 mhz, the high speed sync enable bit, cfr2<11>, should be set. 5 this parameter indicates that the digital synchronization feature canno t overcome phase delays (timing skew) between system cl ock rising edges. if the system clock edges are aligned, the synchronizat ion function should not increase the skew between the two edges.
ad9953 rev. a | page 6 of 32 absolute maximum ratings table 2. parameter rating maximum junction temperature 150c dvdd_i/o (pin 43) 4 v avdd, dvdd 2 v digital input voltage (dvdd_i/o = 3.3 v) C0.7 v to +5.25 v digital input voltage (dvdd_i/o = 1.8 v) C0.7 v to +2.2 v digital output current 5 ma storage temperature C65c to +150c operating temperature C40c to +105c lead temperature (10 sec soldering) 300c ja 38c/w jc 15c/w stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution iout iout must terminate outputs to avdd. do not exceed the output voltage compliance rating. dac outputs dvdd_i/o input digital inputs avoid overdriving digital inputs. forward biasing esd diodes may couple digital noise onto power pins. 03374-0-032 figure 2. equivalent input and output circuits
ad9953 rev. a | page 7 of 32 pin configuration 43 42 41 40 39 38 37 48 47 46 45 44 13 15 16 17 18 19 20 21 22 23 24 i/o update dvdd dgnd avdd agnd avdd agnd osc/refclk osc/refclk crystal out clkmodeselect loop_filter agnd avdd agnd avdd agnd avdd iout avdd iout dacbp agnd osk ps1 ps0 sync_clk sync_in dvdd_i/o sclk dgnd sdio sdo cs iosync reset pwrdwnctl dvdd dgnd agnd agnd agnd avdd agnd avdd agnd avdd ad9953 top view (not to scale) 14 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 03357-0-002 dac_ r set figure 3. 48-lead tqfp/ep note that the exposed paddle on the bottom of the package forms an electrical connection for the dac and must be attached to analog ground. note that pin 43, dvdd_i/o, can be powered to 1.8 v or 3.3 v; however, the dvdd pins (pin 2 and pin 34) can only be powered to 1.8 v.
ad9953 rev. a | page 8 of 32 pin function descriptions table 3. 48-lead tqfp/ep pin no. mnemonic i/o description 1 i/o update i the rising edge transfers the contents of the internal buffer memory to the i/o registers. this pin must be set up and held around the sync_clk output signal. 2, 34 dvdd i digital power supply pins (1.8 v). 3, 33, 42 dgnd i digital power ground pins. 4, 6, 13, 16, 18, 19, 25, 27, 29 avdd i analog power supply pins (1.8 v). 5, 7, 14, 15, 17, 22, 26, 32 agnd i analog power ground pins. 8 osc / refclk i complementary reference clock/oscillator input. when the refclk port is operated in single- ended mode, refclk should be decoupled to avdd with a 0.1 f capacitor. 9 osc/refclk i reference clock/oscillator input. see clock input section for details on the oscillator/refclk operation. 10 crystal out o output of the oscillator section. 11 clkmodeselect i control pin for the oscillator section. when high, the oscillator section is enabled. when low, the oscillator section is bypassed. 12 loop_filter i this pin provides the connection for the external zero compensation network of the refclk multipliers pll loop filter. the network consists of a 1 k resistor in series with a 0.1 f capacitor tied to avdd. 20 iout o complementary dac output. should be biased through a resistor to avdd, not agnd. 21 iout o dac output. should be biased through a resistor to avdd, not agnd. 23 dacbp i dac biasline decoupling pin. a 0.1 f capacitor to agnd is recommended. 24 dac_r set i a resistor (3.92 k nominal) connected from agnd to dac_r set establishes the reference current for the dac. 35 pwrdwnctl i input pin used as an external power-down control (see table 10 for details). 36 reset i active high hardware reset pin. assertion of the reset pin forces the ad9953 to the initial state, as described in the i/o port register map. 37 iosync i asynchronous active high reset of the serial port controller. when high, the current i/o operation is immediately terminated, enabling a new i/o operation to commence once iosync is returned low. if unused, ground this pi n; do not allow this pin to float. 38 sdo o when operating the i/o port as a 3-wire serial port, this pin serves as the se rial data output. when operated as a 2-wire serial port, this pin is unused and can be left unconnected. 39 cs i this pin functions as an active low chip select that allows multiple devices to share the i/o bus. 40 sclk i this pin functions as the serial data clock for i/o operations. 41 sdio i/o when operating the i/o port as a 3-wire serial port , this pin serves as the serial data input only. when operated as a 2-wire serial port, this pin is the bidirectional serial data pin. 43 dvdd_i/o i digital power supply (for i/o cells only, 3.3 v). 44 sync_in i input signal used to synchronize multiple ad 9953s. this input is connected to the sync_clk output of a master ad9953. 45 sync_clk o clock output pin that serves as a synchronizer for external hardware. 46 osk i input pin used to control the direction of the shaped on-off keying function when programmed for operation. osk is synchronous to the sync_c lk pin. when osk is not programmed, this pin should be tied to dgnd. 47, 48 ps0, ps1 i input pin used to select one of the four internal profiles. profile <1:0> are synchronous to the sync_clk pin. any change in these inputs transfer s the contents of the internal buffer memory to the i/o registers (sends an internal i/o update). <49> agnd i the exposed paddle on the bottom of the package is a ground connection for the dac and must be attached to agnd in any board layout.
ad9953 rev. a | page 9 of 32 typical performance characteristics center 100mhz #res bw 3khz vbw 3khz span 200mhz sweep 55.56 s (401 pts) ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 w1 s2 s3 fc aa ref 0dbm pea k log 10db/ atten 10db mkr1 98.0mhz ? 70.68db 1 1r 03374-0-016 marker 100.000000mhz ?70.68db figure 4. f out = 1 mhz fclk = 400 msps, wbsfdr center 100mhz #res bw 3khz vbw 3khz span 200mhz sweep 55.56 s (401 pts) ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 w1 s2 s3 fc aa ref 0dbm pea k log 10db/ atten 10db mkr1 80.0mhz ? 69.12db 1 1r 03374-0-017 marker 80.000000mhz ?69.12db figure 5. f out = 10 mhz, fclk = 400 msps, wbsfdr center 100mhz #res bw 3khz vbw 3khz span 200mhz sweep 55.56 s (401 pts) ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 w1 s2 s3 fc aa ref 0dbm pea k log 10db/ atten 10db mkr1 0hz ? 68.44db 1 1r 03374-0-018 marker 40.000000mhz ?68.44db figure 6. f out = 40 mhz, fclk = 400 msps, wbsfdr center 100mhz #res bw 3khz ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 vbw 3khz span 200mhz sweep 55.56 s (401 pts) w1 s2 s3 fc aa ref 0dbm pea k log 10db/ atten 10db mkr1 80.0mhz ? 61.55db 1 1r marker 80.000000mhz ?61.55db 03374-0-019 figure 7. f out = 80 mhz fclk = 400 msps, wbsfdr center 100mhz #res bw 3khz ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 vbw 3khz span 200mhz sweep 55.56 s (401 pts) w1 s2 s3 fc aa ref 0dbm pea k log 10db/ atten 10db mkr1 40.0mhz ?56.2db 1 1r marker 40.000000mhz ?56.2db 03374-0-020 figure 8. f out = 120 mhz, fclk = 400 msps, wbsfdr center 100mhz #res bw 3khz ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 vbw 3khz span 200mhz sweep 55.56 s (401 pts) w1 s2 s3 fc aa ref 0dbm pea k log 10db/ atten 10db mkr1 0hz ? 53.17db 1 1r marker 80.000000mhz ?53.17db 03374-0-021 figure 9. f out = 160 mhz, fclk = 400 msps, wbsfdr
ad9953 rev. a | page 10 of 32 center 1.105mhz #res bw 30hz ?100 vbw 30hz span 2mhz sweep 199.2 s (401 pts) ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 w1 s2 s3 fc aa st ref ?4dbm pea k log 10db/ atten 10db mkr1 1.105mhz ?5.679dbm 1 03374-0-022 marker 1.105000mhz ?5.679dbm figure 10. f out = 1.1 mhz, fclk = 400 msps, nbsfdr, 1 mhz center 10mhz #res bw 30hz ?100 vbw 30hz span 2mhz sweep 199.2 s (401 pts) ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 w1 s2 s3 fc aa ref 0dbm pea k log 10db/ atten 10db mkr1 85khz ?93.01db 1 1r 03374-0-023 marker 40.000000mhz ?56.2db figure 11. f out = 10 mhz, fclk = 400 msps, nbsfdr, 1 mhz center 39.9mhz #res bw 30hz ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 vbw 30hz span 2mhz sweep 199.2 s (401 pts) w1 s2 s3 fc aa ref 0dbm pea k log 10db/ atten 10db mkr1 39.905mhz ?5.347dbm 1 03374-0-024 marker 39.905000mhz ?5.347dbm figure 12. f out = 39.9 mhz, fclk = 400 msps, nbsfdr, 1 mhz center 80.25mhz #res bw 30hz ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 vbw 30hz span 2mhz sweep 199.2 s (401 pts) w1 s2 s3 fc aa st ref ?4dbm pea k log 10db/ atten 10db mkr1 80.301mhz ?6.318dbm 1 marker 80.301000mhz ?6.318dbm 03374-0-025 figure 13. f out = 80.3 mhz, fclk = 400 msps, nbsfdr, 1 mhz center 120.2mhz #res bw 30hz ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 vbw 30hz span 2mhz sweep 199.2 s (401 pts) w1 s2 s3 fc aa st ref ?4dbm pea k log 10db/ atten 10db mkr1 120.205mhz ?6.825dbm 1 marker 120.205000mhz ?6.825dbm 03374-0-026 figure 14. f out = 120.2 mhz, fclk = 400 msps, nbsfdr, 1 mhz center 160.5mhz #res bw 30hz ?100 vbw 30hz span 2mhz sweep 199.2 s (401 pts) ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 w1 s2 s3 fc aa st ref ?4dbm pea k log 10db/ atten 10db mkr1 600khz ?0.911db 1 center 160.5000000mhz 03374-0-027 figure 15. f out = 160 mhz, fclk = 400 msps, nbsfdr, 1 mhz
ad9953 rev. a | page 11 of 32 figure 16. residual phase noise with f out = 159.5 mhz, f clk = 400 msps (green), 4 100 msps (red), and 20 20 msps (blue) ch1 200mv 1 it 4.0ps/pt 3.1ns m 200ps 20.0gs/s a ch1 708mv 03374-0-031 t 1 = 3.156ns t 2 = 3.04ns t = ?116.0ps 1/ t = ?8.621ghz figure 17. residual peak-to-peak jitter of dds and comparator operating together at 160 mhz figure 18. residual phase noise with f out = 9.5 mhz, f clk = 400 msps (green), 4 100 msps (red), and 20 20 msps (blue) ref2 200mv 500ns it 10.0ps/pt ?100ps m 500ps 20.0gs/s a ch1 708mv r2 r1 03374-0-030 fall (r1) = 396.4ps rise(r2) = 464.3ps figure 19. comparator rise and fall time at 160 mhz
ad9953 rev. a | page 12 of 32 theory of operation component blocks dds core the output frequency ( f o ) of the dds is a function of the frequency of the system clock (sysclk), the value of the frequency tuning word ( ftw ), and the capacity of the accumulator (2 32 , in this case). the exact relationship is given below with f s defined as the frequency of sysclk. ?? ?? 31 32 2 0 2/ ?? ? ftw with fftwf s o ?? ?? 1C2 2 2/C1 32 31 32 ?? ?? ftw with ftw ff so the value at the output of the phase accumulator is translated to an amplitude value via the cos(x) functional block and routed to the dac. in certain applications, it is desirable to force the output signal to zero phase. simply setting the ftw to 0 does not accomplish this; it only results in the dds core holding its current phase value. thus, a control bit is required to force the phase accumulator output to zero. at power-up, the clear phase accumulator bit is set to logic 1, but the buffer memory for this bit is cleared (logic 0). therefore, upon power-up, the phase accumulator will remain clear until the first i/o update is issued. phase-locked loop (pll) the pll allows multiplication of the refclk frequency. control of the pll is accomplished by programming the 5-bit refclk multiplier portion of control function register no. 2, bits <7:3>. when programmed for values ranging from 0x04 to 0x14 (4 decimal to 20 decimal), the pll multiplies the refclk input frequency by the corresponding decimal value. however, the maximum output frequency of the pll is restricted to 400 mhz. whenever the pll value is changed, the user should be aware that time must be allocated to allow the pll to lock (approximately 1 ms). the pll is bypassed by programming a value outside the range of 4 to 20 (decimal). when bypassed, the pll is shut down to conserve power. clock input the ad9953 supports various clock methodologies. support for differential or single-ended input clocks and enabling of an on- chip oscillator and/or a phase-locked loop (pll) multiplier is all controlled via user programmable bits. the ad9953 may be configured in one of six operating modes to generate the system clock. the modes are configured using the clkmodeselect pin, cfr1<4>, and cfr2<7:3>. connecting the external pin clkmodeselect to logic high enables the on-chip crystal oscillator circuit. with the on-chip oscillator enabled, users of the ad9953 connect an external crystal to the refclk and refclkb inputs to produce a low frequency reference clock in the range of 20 mhz to 30 mhz. the signal generated by the oscillator is buffered before it is delivered to the rest of the chip. this buffered signal is available via the crystal out pin. bit cfr1<4> can be used to enable or disable the buffer, turning on or off the system clock. the oscillator itself is not powered down in order to avoid long start-up times associated with turning on a crystal oscillator. writing cfr2<9> to logic high enables the crystal oscillator output buffer. logic low at cfr2<9> disables the oscillator output buffer. connecting clkmodeselect to logic low disables the on-chip oscillator and the oscillator output buffer. with the oscillator disabled, an external oscillator must provide the refclk and/or refclkb signals. for differential operation, these pins are driven with complementary signals. for single- ended operation, a 0.1 f capacitor should be connected between the unused pin and the analog power supply. with the capacitor in place, the clock input pin bias voltage is 1.35 v. in addition, the pll may be used to multiply the reference frequency by an integer value in the range of 4 to 20. table 4 summarizes the clock modes of operation. note that the pll multiplier is controlled via the cfr2<7:3> bits, independent of the cfr1<4> bit. table 4. clock input modes of operation cfr1<4> clkmodeselect cfr2<7:3> oscillator enabled? system clock frequency range (mhz) low high 3 < m < 21 yes f clk = f osc m 80 < f clk < 400 low high m < 4 or m > 20 yes f clk = f osc 20 < f clk < 30 low low 3 < m < 21 no f clk = f osc m 80 < f clk < 400 low low m < 4 or m > 20 no f clk = f osc 10 < f clk < 400 high x x no f clk = 0 n/a
ad9953 rev. a | page 13 of 32 out set i r /19.39 = dac output the ad9953 incorporates an integrated 14-bit current output dac. unlike most dacs, this output is referenced to avdd, not agnd. two complementary outputs provide a combined full-scale output current (i out ). differential outputs reduce the amount of common-mode noise that might be present at the dac output, offering the advantage of an increased signal-to-noise ratio. the full-scale current is controlled by an external resistor (r set ) connected between the dac_r set pin and the dac ground (agnd_dac). the full-scale current is proportional to the resistor value as follows: the maximum full-scale output current of the combined dac outputs is 15 ma, but limiting the output to 10 ma provides the best spurious-free dynamic range (sfdr) performance. the dac output compliance range is avdd + 0.5 v to avdd C 0.5 v. voltages developed beyond this range will cause excessive dac distortion and could potentially damage the dac output circuitry. proper attention should be paid to the load termination to keep the output voltage within this compliance range. serial io port the ad9953 serial port is a flexible, synchronous serial communications port that allows easy interface to many industry- standard microcontrollers and microprocessors. the serial i/o port is compatible with most synchron ous transfer formats, including both the motorola 6905/11 spi? and intel? 8051 ssr protocols. the interface allows read/write access to all registers that configure the ad9953. msb first or lsb first transfer formats are supported. the ad9953s serial interface port can be configured as a single pin i/o (sdio), which allows a 2-wire interface or two unidirectional pins for in/out (sdio/sdo), which in turn enables a 3-wire interface. two optional pins, iosync and cs , enable greater flexibility for system design in the ad9953. register map and descriptions the register map is listed in table 5 .
ad9953 rev. a | page 14 of 32 able 5. register map s) it ange sb) it 7 it 6 it 5 it 3 it 2 it 1 sb) it 0 default value t register name (serial addres b r (m b b b bit 4 b b b (l b or profile control function <7:0> ital power- p power- power- input power- r- ar sweep no clk out used register no.1 (cfr1) (0x00) dig down com down dac down clock down external powe down mode line dwell sync_ disable not 0x00 <15:8> l @ i/o ud a a lsb first 0x00 oad srr autoclr freq. accum. autoclr phase accum. enable sine output clear freq. ccum. clear phase ccum. sdio input only <23:16> s n n n n d not used 0x00 automatic sync enable oftware manual sync linear sweep enable ot used ot used ot used ot use <31:24> enable d nal profile control <2:0> load arr @ i/o ud osk enable osk keying 0x00 ram ram est. is phase word inter auto control function n <7:0> 0x00 or 0x01, or 0x02 or 0x03: bypass multiplier 0x04 to 0x14: 4 to 20 multiplication vco range charge pump <1:0> 0x00 register o. 2 (cfr2) (0x01) refclk m ultiplier current <15:8> not used high speed manual crysta out pin not used 0x00 sync enable hardware sync enable l active <23:16> not used 0x18 amplitude scale factor <7:0> amplitude scale facto r <7: 0x00 (asf) (0x02) r registe 0> <15:8> auto ramp rate speed control <1:0> amplitude scale factor register <13:8> 0x00 amplitude ra e <7:0> amplitude ramp rate register <7:0> 0x00 mp rat (arr) (0x03) fr y <7:0> frequency tuning word no. 0 <7:0> 0x00 equenc tuning word (ftw0) (0x04) <15:8> frequency tuning word no. 0 <15:8> 0x00 <23:16> f requency tuning word no. 0 <23:16> 0x00 <31:24> frequency tuning word no. 0 <31:24> 0x00 phase fset wor of d (pow0) (0x05) <7:0> phase offset word no. 0 <7:0> 0x00 <15:8> not used<1:0> no. 0 <13:8> phase offset word 0x00 f frequency tun 0x00 requency tuning word (ftw1) (0x06) <7:0> ing word no. 1 <7:0> <15:8> f requency tuning word no. 1 <15:8> 0x00 <23:16> f requency tuning word no. 1 <23:16> 0x00 <31:24> frequency tuning word no. 1 <31:24> 0x00
ad9953 rev. a | page 15 of 32 register name (serial address) bit range (msb) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 (lsb) bit 0 default value or profile ram segment control rd no. 0 (rscw0) (0x07) <7:0> ram segment 0 m de control <2:0> no d ell active ram segment 0 beginning address <9:6> s0 = 0 ps1 = 0 wo o w p <15:8> ram segment 0 beginning address <5:0> ram segment 0 final address <9:8> ps0 = 0 ps1 = 0 <23:16> ram segment 0 final address <7:0> ps0 = 0 ps1 = 0 <31:24> ram segment 0 address ramp rate <15:8> ps0 = 0 ps1 = 0 <39:32> ram segment 0 address ramp rate <7:0> ps0 = 0 ps1 = 0 ram segment control word no. 1 (rscw1) (0x08) <7:0> ram segment 1 mode control <2:0> no dwell active ram segment 1 beginning address <9:6> ps0 = 1 ps1 = 0 <15:8> ram segment 1 beginning address <5:0> 9:8> ram segment 1 final address < ps0 = 1 ps1 = 0 <23:16> ram segment 1 final address <7:0> ps0 = 1 ps1 = 0 <31:24> ram segment 1 address ramp rate <15:8> ps0 = 1 ps1 = 0 <39:32> ram segment 1 address ramp rate <7:0> ps0 = 1 ps1 = 0 ram segment control word no. 2 (rscw2) (0x09) <7:0> r < cti address <9:6> am segment 2 mode control 2:0> no dwell a ve ram segment 2 beginning ps0 = 0 ps1 = 1 <15:8> ram s ram s egment 2 beginning address <5:0> egment 2 final address <9:8> ps0 = 0 ps1 = 1 <23:16> ram segment 2 final address <7:0> ps0 = 0 ps1 = 1 <31:24> ram segment 2 address ramp rate <15:8> ps0 = 0 ps1 = 1 <39:32> ram segment 2 address ramp rate <7:0> ps0 = 0 ps1 = 1 ram segment control word no. 3 (rscw3) (0x0a) <7:0> ram segment 3 mode control <2:0> no dwell active ram segment 3 beginning address <9:6> ps0 = 1 ps1 = 1 <15:8> ram segment 3 beginning address <5:0> ram segment 3 final address <9:8> ps0 = 1 ps1 = 1 <23:16> ram segment 3 final address <7:0> ps0 = 1 ps1 = 1 <31:24> ram segment 3 address ramp rate <15:8> ps0 = 1 ps1 = 1 <39:32> ram segment 3 address ramp rate <7:0> ps0 = 1 ps1 = 1 ram (0x0b) (rea e out ram ram [1023:0] <31:0> d instructions: writ register data)
control register bit descriptions control function register. no. 1 (cfr1) the cfr1 is used to control the various functions, features, and modes of the ad9953. the functionality of each bit is below. cfr1<31>: ram enable bit cfr1<31> = 0 (default). the ram is powered down to conserve power. single-tone mode of operation is active. cfr1<31> = 1. if cfr1<31> is active, the ram is enabled for operation. access control for normal operation is controlled via the mode control bits of the rscw for the current profile. cfr1<30>: ram destination bit cfr1<30> = 0 (default). if cfr1<31> is active, a logic 0 on the ram destination bit (cfr1<30> = 0) configures the ad9953 such that the ram output drives the phase accumulator (i.e., the frequency tuning word). if cfr1<31> is inactive, cfr1<30> is a dont care. cfr1<30> = 1. if cfr1<31> is active, a logic 1 on the ram destination bit (cfr1<30> = 1) configures the ad9953 such that the ram output drives the phase-offset adder (i.e., sets the phase offset of the dds core). cfr1<29:27>: not used cfr1<26>: amplitude ramp rate load control bit cfr1<26> = 0 (default). the amplitude ramp rate timer is loaded only upon timeout (timer == 1) and is not loaded due to an i/o update input signal. cfr1<26> = 1. the amplitude ramp rate timer is loaded upon timeout (timer == 1) or at the time of an i/o update input signal. cfr1<25>: shaped on-off keying enable bit cfr1<25> = 0 (default). shaped on-off keying is bypassed. cfr1<25> = 1. shaped on-off keying is enabled. when enabled, cfr1<24> controls the mode of operation for this function. cfr1<24>: auto shaped on-off keying enable bit (only valid when cfr1<25> is active high) cfr1<24> = 0 (default). when cfr1<25> is active, a logic 0 on cfr1<24> enables the manual shaped on-off keying operation. each amplitude sample sent to the dac is multiplied by the amplitude scale factor. see the shaped on-off keying section for details. cfr1<24> = 1. when cfr1<25> is active, a logic 1 on cfr1<24> enables the auto shaped on-off keying operation. toggling the osk pin high will cause the output scalar to ramp up from zero scale to the amplitude scale factor at a rate deter- mined by the amplitude ramp rate. toggling the osk pin low will cause the output to ramp down from the amplitude scale factor to zero scale at the amplitude ramp rate. see the shaped on-off keying section for details. cfr1<23>: automatic synchronization enable bit cfr1<23> = 0 (default). the automatic synchronization feature of multiple ad9953s is inactive. cfr1<23> = 1. the automatic synchronization feature of multiple ad9953s is active. the device will synchronize its internal synchronization clock (sync_clk) to align to the signal present on the sync_in input. see the synchronizing multiple ad9953s section for details. cfr1<22>: software manual synchronization of multiple ad9953s cfr1<22> = 0 (default). the manual synchronization feature is inactive. cfr1<22> = 1. the software controlled manual synchroniza- tion feature is executed. the sync_clk rising edge is advanced by one sync_clk cycle and this bit is cleared. to advance the rising edge multiple times, this bit needs to be set for each advance. see the synchronizing multiple ad9953s section for details. cfr1<21:14>: not used cfr1<13>: auto-clear phase accumulator bit cfr1<13> = 0 (default). the current state of the phase accumula- tor remains unchanged when the frequency tuning word is applied. cfr1<13> = 1. this bit automatically synchronously clears (loads 0s into) the phase accumulator for one cycle upon reception of an i/o update signal. cfr1<12>: sine/cosine select bit cfr1<12> = 0 (default). the angle-to-amplitude conversion logic employs a cosine function. cfr1<12> = 1. the angle-to-amplitude conversion logic employs a sine function. cfr1<11>: not used cfr1<10>: clear phase accumulator cfr1<10> = 0 (default). the phase accumulator functions as normal. cfr1<10> = 1. the phase accumulator memory elements are cleared and held clear until this bit is cleared.
ad9953 rev. a | page 17 of 32 ing mode). igured as ctive. 1. all non-io digital functionality is suspended, : not used down bit he clock input circuitry is enabled for d the external power-down mode ode, high, the digital logic red down. the dac bias the ctl ons are powered down. this includes ake a significant amount of time to ync_clk disable bit static logic 0 ate to keep noise generated by the digital circuitry at a s ming. ntrol the various functions, features, and og sections ot used bit o use the auto- e for sync_clk inputs beyond 50 mhz, chronizing multiple ad9953s ff. nc function is enabled. sync_in pin will cle. unlike the software manual sync enable bit, this is red. see the n for details. , t y. the oscillator will respond to crystals in ord controls the multiplier value out of the clock- k. valid values are decimal 4 to 20 (0x04 to tside this range will bypass the clock op (pll) section for details. nge of 100 mhz to 250 mhz. when cfr2<2> == 1, the vco operates in a range of 250 mhz to 400 mhz. cfr1<9>: sdio input only cfr1<9> = 0 (default). the sdio pin has bidirectional operation (2-wire serial programm cfr1<9> = 1. the serial data i/o pin (sdio) is conf an input only pin (3-wire serial programming mode). cfr1<8>: lsb first cfr1<8> = 0 (default). msb first format is active. cfr1<8> = 1. the serial interface accepts serial data in lsb first format. cfr1<7>: digital power-down bit cfr1<7> = 0 (default). all digital functions and clocks are a cfr1<7> = lowering the power significantly. cfr1<6> cfr1<5>: dac power-down bit cfr1<5> = 0 (default). the dac is enabled for operation. cfr1<5> = 1. the dac is disabled and is in its lowest power dissipation state. cfr1<4>: clock input power- cfr1<4> = 0 (default). t operation. cfr1<4> = 1. the clock input circuitry is disabled an device is in its lowest power dissipation state. cfr1<3>: cfr1<3> = 0 (default). the external power-down mode selected is the rapid recovery power-down mode. in this m when the pwrdwnctl input pin is and the dac digital logic are powe circuitry, pll, oscillator, and clock input circuitry are not powered down. cfr1<3> = 1. the external power-down mode selected is full power-down mode. in this mode, when the pwrdwn ncti input pin is high, all fu the dac and pll, which t power up. cfr1<2>: not used cfr1<1>: s cfr1<1> = 0 (default). the sync_clk pin is active. e sync_clk pin assumes a cfr1<1> = 1. th st minimum. however, the synchronization circuitry remain active (internally) to maintain normal device ti cfr1<0>: not used, leave at 0 control function register no. 2 (cfr2) the cfr2 is used to co modes of the ad9953, primarily related to the anal of the chip. cfr2<23:12>: n cfr2<11>: high speed sync enable cfr2<11> = 0 (default). the high speed sync enhancement is off. cfr2<11> = 1. the high speed sync enhancement is on. this bit should be set when attempting t synchronization featur (200 msps sysclk). see the syn section for details. cfr2<10>: hardware manual sync enable bit cfr2<10> = 0 (default). the hardware manual sync function is o cfr2<10> = 1. the hardware manual sy while this bit is set, a rising edge on the cause the device to advance the sync_clk rising edge by one refclk cy bit does not self clear. once the hardware manual sync mode enabled, it will stay enabled until this bit is clea synchronizing multiple ad9953s sectio cfr2<9>: crystal out enable bit cfr2<9> = 0 (default). the crystal out pin is inactive. cfr2<9> = 1. the crystal out pin is active. when active the crystal oscillator circuitry output drives the crystal ou pin, which can be connected to other devices to produce a reference frequenc the range of 20 mhz to 30 mhz. cfr2<8>: not used cfr2<7:3>: reference clock multiplier control bits this 5-bit w multiplier (pll) bloc 0x14). values entered ou multiplier. see the phase-locked lo cfr2<2>: vco range control bit this bit is used to control the range setting on the vco. when cfr2<2> == 0 (default), the vco operates in a ra
ad9953 rev. a | page 18 of 32 e charge <1:0>, sets the charge pump bit added (01, 10, ump current: (asf) p rate speed value ed in the output shaped , 10, 11}, the al osk mode, asf<15:14> has no effect. ectly. if the osk o effect he core. e output of the phase e output signal. the mula: cfr2<1:0>: charge pump current control bits these bits are used to control the current setting on th pump. the default setting, cfr2 current to the default value of 75 a. for each 11), 25 a of current is added to the charge p 100 a, 125 a, and 150 a. other register descriptions amplitude scale factor the asf register stores the 2-bit auto ram and the 14-bit amplitude scale factor us keying (osk) operation. in auto osk operation, asf <15:14> tells the osk block how many amplitude steps to take for each increment or decrement. for asf<15:14> = {00, 01 increment/decrement is set to {1, 2, 4, 8}, respectively. asf <13:0> sets the maximum value achievable by the osk internal multiplier. in manu asf <13:0> provides the output scale factor dir enable bit is cleared, cfr1<25> = 0, this register has n on device operation. amplitude ramp rate (arr) the arr register stores the 8-bit amplitude ramp rate used in the auto osk mode. this register programs the rate at which the amplitude scale factor counter increments or decrements. if the osk is set to manual mode, or if osk enable is cleared, this register has no effect on device operation. frequency tuning word 0 (ftw0) the frequency tuning word is a 32-bit register that controls t rate of accumulation in the phase accumulator of the dds its specific role is dependent on the device mode of operation. phase offset word (pow) the phase offset word is a 14-bit register that stores a phase offset value. this offset value is ad ded to th he current phase of th accumulator to offset t exact value of phase offset is given by the following for ? ? ? ? ? ? = 360 2 14 pow ram segment control words (rscw0, rscw1, rscw and rscw3) 2, r1<21> is clear, ent o-dwell bit. am segment address ramp rate, rscw<39:24> or ram modes that step through address values, such as sync_clk ent. the order in which the bits e bits must be written. he write operation is more its 5>, is the msb of the final address value. <7:5> eping profiles. in ginning address and dwell there d. operations from and to the ram are valid, but they cannot occur simultaneously. write operations fro the serial i/o port have precedence, and if an attempt to write to ram is made in multiple ways, dictated by the modes of d <7:5> or or the m destina- utput e offset control word(s) for the device. when cfr1<30> is logic 0 (default condition), the ram output is connected to the when the linear sweep enable bit cf registers 0x07, 0x08, 0x09, and 0x0a act as the ram segm control words for each of the ram segments. each of the ram segment control words is comprised of a ram segment address ramp rate, a final address value, a beginning address value, a am segment mode control, and a n r r f ramping, this 16-bit word defines the number of cycles the ram controller dwells at each address. a value of 0 is invalid. any other value from 1 to 65535 may be used. ram segment final address rscw<9:8>, rscw<23:16> this discontinuous 10-bit sequence defines the final address value for the given ram segm are listed is the order in which th rscw<23>, even though during t significant than rscw<9>, is only the third msb of the final address value. rscw<9>, even though it comes later in the rscw than rscw<23>, is the msb of the final address value. ram segment beginning address rscw<3:0>, <15:10> this discontinuous 10-bit sequence defines the final address value for the given ram segment. the order in which the b are listed is the order in which the bits must be written. rscw<15>, even though during the write operation is more significant than rscw<3>, is on ly the fifth msb of the final address value. rscw<3>, even though it comes later in the rscw than rscw<1 ram segment mode control rscw this 3-bit sequence determines the ram segments mode of operation. there are only five possible ram modes, so only values of 0 to 5 are valid. see table 6 to determine the bit combination for various ram modes. ram segment no-dwell bit rscw<4> this bit sets the no-dwell feature of swe profiles that sweep from a defined beginning to a defined end, the ram controller can either dwell at the final address until the next profile is selected or, when this bit is set, the ram controller will return to the be until the next profile is selecte ram the ad9953 incorporates a 1024 32 block of sram. the ram is a bidirectional single port. both read and write m during a read operation, the read operation will be halted. the ram is controlled operation described in the ram segment control wor as well as data in the control function register. read/write control for the ram will be described for each mode supported. when the ram enable bit (cfr1<31>) is set, the ram output optionally drives the input to the phase accumulat phase offset adder, depending on the state of the ra tion bit (cfr1<30>). if cfr1<30> is a logic 1, the ram o is connected to the phase offset adder and supplies the phas
ad9953 rev. a | page 19 of 32 s 0x05) put w ent m, s . ct pins ps<1:0>. ial to the ending address. e the serial port to expect bit words. the first 32 bits would be parsed as a word ed n). ase r. -tone fsk, the user programs each ram segment or e adder (<31:18>). s dest irect it m odes that enable the memory, bit controls whether the ram output ulator or the phase offset adder. r finishes a cycle, the ram address generator crements to the next address and the timer reloads the ramp te bits and begins a new countdown cycle. this sequence ontinues until the ram address generator has incremented to n address equal to the ram segment final address bits of the urrent rscw. input of the phase accumulator and supplies the frequency tuning word(s) for the device. when the ram output drives the phase accumulator, the phase offset word (pow, addres drives the phase-offset adder. similarly, when the ram out , drives the phase offset adder, the frequency tuning word (ft address 0x04) drives the phase accumulator. when cfr1<31> is logic 0, the ram is inactive unless being written to via the serial port. the power-up state of the ad9953 is the single-tone mode, in which the ram enable bit is inactive. the ram is segmented into four unique slices controlled by the profile<1:0 input pins. rolled > ram controlled modes of operation direct switch mode direct switch mode enables fsk or psk modulation. the ad9953 is programmed for direct switch mode by writing the ram enable bit true and programming the ram segment mode control bits of each desired profile to logic 000(b). this mode simply reads the ram contents at the ram segment beginning address for the current profile. no address ramping is enabled in direct switch mode. to perform 4 all ram writes/reads, unless otherwise specified, are cont by the profile<1:0> input pins and the respective ram segm control word. the ram can be written to during normal operation, but any i/o operation that commands the ram to be written immediately suspends read operation from the ra causing the current mode of operation to be nonfunctional. thi excludes single-tone mode, as the ram is not read in this mode writing the ram is accomplished as follows. after configuring the desired ram segment control words, the desired ram c segment must be selected via the profile sele during the instruction byte, write the address for the ram, 0x0b. the serial port and ram controller will work in conjunction to determine the width of the profile and the ser port will accept the defined number of 32-bit words sequentially from the beginning address consider the following example: ? the ram segment control word 1 lists the beginning ram address at 256 and the ending address at 511. ? ps0 = 1 and ps1 = 0. ? the instruction byte is 10001001. the ram controller would configur 256 32- and sent to ram address 256. the next 32 bits would be pars and sent to 257, and so forth, all the way through until the 256 word was sent (grand total of 8,192 data bits in this operatio modes of operation single-tone mode in single-tone mode, the dds core uses a single tuning word. whatever value is stored in ftw0 is supplied to the phase accumulator. this value can only be changed manually, which is done by writing a new value to ftw0 and by issuing an i/o update. phase adjustment is possible through the ph offset registe ontrol word for direct switch mode and a unique beginning address value. in addition, the ram enable bit is written true, which enables the ram, and the ram destination bit is written false, setting the ram output to be the frequency tuning word. the profile<1:0> inputs are the 4-tone fsk data inputs. when the profile is changed, the frequency tuning word stored in the new profile is loaded into the phase accumulator and is used to increment the currently stored value in a phase continuous f ashion. the phase offset word drives the phase-offset adder. two-tone fsk is accomplished by using only one profile pin f data. programming the ad9953 for psk modulation is similar to fsk except the ram destination bit is set to a logic 1, enabling the ram output to drive the phase offset adder. the ftw0 drives the input to the phase accumulator. toggling the profile pins changes (modulates) the current phase value. the upper 14 bits of the ram drive the phas bit <17:0> of the ram output are unused when the ram ination bit is set. the no-dwell bit is a dont care in d sw ch mode. ra p-up mode ramp-up mode, in conjunction with the segmented ram capability, allows up to four different sweep profiles to be programmed into the ad9953. the ad9953 is programmed for ramp-up mode by writing the ram enable bit true and programming the ram mode control bits of each profile to be used to logic 001(b). as in all m the ram destination drives the phase accum upon starting a sweep (via an i/o update or change in profile bits), the ram address generator loads the ram segment beginning address bits of the current rscw, driving the ram output from this address, and the ramp rate timer loads the ram segment address ramp rate bits. when the ramp rate time in ra c a c
ad9953 rev. a | page 20 of 32 address generator the generator stops incrementing as the te e phase accumulator remains al as l control bits of rscw0 to logic 010(b). in bidirectional > r segment address ramp rate bits. the ram e beginning address, and the ramp rate timer g- te e i/o t. enera- r in f the mp as rol the ram in the ies. for continuous bidirectional ramp the ram address generator loads the ram ts of the current rscw and the its. the ramp te timer begins to count down to 1. when the ramp rate timer ompletes a cycle, the ram address generator increments to the if the no-dwell bit is clear when the ram equals the final address, terminal frequency has been reached. the sweep is comple and does not restart until an i/o update or change in profile is detected to enable another sweep from the beginning to the final ram address as described above. if the no-dwell bit is set when the ram address generator equals the final address, after the next ramp rate timer cycle the phase accumulator is cleared. th cleared until another sweep is initiated via an i/o update input or change in profile. another application for ramp-up mode is nonsymmetrical fsk modulation. with the ram configured for two segments, using the profile<0> bit as the data input allows nonsymmetrical ramped fsk. bidirectional ramp mode bidirectional ramp mode allows the ad9953 to offer a symme- trical sweep between two frequencies using the profile<0> sign the control input. the ad9953 is programmed for bidirectiona ramp mode by writing the ram enable bit true and the ram mode ramp mode, the profile<1> input is ignored and the profile<0 input is the ramp direction indicator. in this mode, the memory is not segmented and uses only a single beginning and final address. the address registers that affect the control of the ram are located in the rscw associated with profile 0. upon entering this mode (via an i/o update or changing profile<0>), the ram address generator loads the ram seg- ment beginning address bits of rscw0 and the ramp rate time loads the ram drives data from th begins to count down to 1. while operating in this mode, to gling the profile<0> pin does not cause the device to genera an internal i/o update. when the profile<0> pin is acting as the ramp direction indicator, any transfer of data from th buffers to the internal registers can only be initiated by a rising edge on the i/o update pin. ram address control now is a function of the profile<0> inpu when the profile<0> bit is a logic 1, the ram address g tor increments to the next address when the ramp rate time completes a cycle (and reloads to start the timer again). as the ramp-up mode, this sequence continues until the ram address generator has incremented to an address equal to the final address as long as the profile<0> input remains high. i profile<0> input goes low, the ram address generator imme- diately decrements and the ramp rate timer is reloaded. the ram address generator will continue to decrement at the ra rate period until the ram address is equal to the beginning address as long as the profile<0> input remains low. the sequence of ramping up and down is controlled via the profile<0> input signal for as long as the part is programmed into this mode. the no-dwell bit is a dont care in this mode is all data in the ram segment control words associated with profiles 1, 2, and 3. only the information in the ram segment control word for profile 0 is used to cont bidirectional ramp mode. continuous bidirectional ramp mode continuous bidirectional ramp mode allows the ad9953 to offer an automatic symmetrical sweep between two frequenc the ad9953 is programmed mode by writing the ram enable bit true and the ram mode control bits of each profile to be used to logic 011(b). upon entering this mode (via an i/o update or changing profile<1:0>), segment beginning address bi ramp rate timer loads the ram segment address ramp rate bits. the ram drives data from the beginning address, and the ramp rate timer begins to count down to 1. when the ramp rate timer completes a cycle, the ram address generator increments to the next address, and the timer reloads the ramp rate bits and continues counting down. this sequence continues until the ram address generator has incremented to an address equal to the ram segment final address bits of the current rscw. upon reaching this terminal address, the ram address generator will decrement in value at the ramp rate until it reaches the ram segment beginning address. upon reaching the beginning address, the entire sequence repeats. the entire sequence repeats for as long as the part is programmed for this mode. the no-dwell bit is a dont care in this mode. in general, this mode is identical in control to the bidirectional ramp mode except the ramp up and down is automatic (no external control via the profile<0> input) and switching profiles is valid. once in this mode, the address generator ramps from the beginning address to the final address, then back to the beginning address at the rate programmed into the ramp rate register. this mode enables generation of an automatic saw tooth sweep characteristic. continuous recirculate mode continuous recirculate mode allows the ad9953 to offer an automatic, continuous unidirectional sweep between two frequencies. the ad9953 is programmed for continuous recirculate mode by writing the ram enable bit true and the ram mode control bits of each profile to be used to logic 100(b). upon entering this mode (via an i/o update or changing profile<1:0>), the ram address generator loads the ram segment beginning address bits of the current rscw and the ramp rate timer loads the ram segment address ramp rate b the ram drives data from the beginning address, and ra c
ad9953 rev. a | page 21 of 32 n fied ram is r notes next address, and the timer reloads the ramp rate bits and continues counting down. this sequence continues until the ram address generator has incremented to an address equal to the ram segment final address bits of the current rscw. upo reaching this terminal address, the ram address generator reloads the ram segment beginning address bits and the sequence repeats. the sequence of circulating through the speci addresses repeats for as long as the part is programmed for th mode. the no-dwell bit is a dont care in this mode. ram controlled modes of operation notes and summary notes: 1. the user must ensure that the beginning address is lowe than the final address. 2. changing profiles or issuing an i/o update automatically terminates the current sweep and starts the next sweep. 3. setting the ram destination bit true such that the ram output drives the phase offset adder is valid. while the above discussion describes a frequency sweep, a phase sweep operation is also available. the ad9953 offers five modes of ram controlled operation (see table 6 ). table 6. ram modes of operation rscw<7:5> (binary) mode 000 direct switch no sweeping, p valid, no dwell invalid rofiles 001 ramp up sweeping, profiles valid, no dwell valid 010 bidirectional ramp sweeping, profile <0> direction control bit, n dwell invalid is a o 011 continuous bidirectional ramp sweeping, profiles v no dwell invalid alid, 100 continuous recirculate sweeping, profiles valid no dwell invalid , 101, 110, 111 open invalid modedefault to direct switch internal profile control the ad9953 offers a mode in which a composite frequency sweep can be built, for which the timing control is software here s am address generator has exhausted the mode description programmable. the internal profile control capability disen- gages the profile<1:0> pins and enables the ad9953 to take control of switching between profiles. modes are defined that allow continuous or single burst profile switches for three combinations of profile selection bits. these are listed in table 7 . when any of the cfr1<29:27> bits are active, the internal profile control mode is engaged. internal profile control is only valid when the device is operating in ram mode. t is no internal profile control for linear sweeping operations. when the internal profile control mode is engaged, the ram segment mode control bits are dont care and the device operates all profiles as if these mode control bits were programmed for ramp-up mode. switching between profile occurs when the r me mory contents for the current profile. ta ble 7. internal profile control cfr1<29:27> (binary) 000 internal control inactive 001 internal control active, single burst, activate profile 0, then 1, then stop 010 internal control active, single burst, activate profile 0, then 1, then 2, then stop 011 te internal control active, single burst, activa profile 0, then 1, then 2, then 3, then stop 100 internal control active, continuous, activate profile 0, then 1, then loop starting 0 101 e , then loop starting 0 internal control active, continuous, activat profile 0, then 1, then 2 110 internal control active, continuous, activate profile 0, then 1, then 2, then 3, then loop starting 0 111 invalid gle b a sin exec urst mo ich th uted once. fo ume th d mp-up mod fr1<29:2 logic 010(b). upon receiving an i/o u ernal ol logic sign to begi mode sequence fo e 0. upon rea final address value for profile 0, the de ally es to profil s execu sequence. upon r m se s value rofile 1, the de tically sw ns executing sequen add r profile er a mposite sw suing another i/o update restarts the burst process. control mode is one in which the de is one in wh r example, ass e composite sweep is e device is programme for ra e and the c 7> bits are written to pdate, the int contr als the device r profil n executing the ramp-up ching the ram segment vice automatic switch e 1 and begin eaching the ra ting that ramp-up gment final addres for p begi vice automa that ramp-up lue fo itches to profile 2 and ce. when the ram segment final sequence is ov ress va nd the co 2 is reached, the eep has completed. is a continuous internal profile composite sweep is continuously executed for as long as the device is programmed into that mode. using the example above, except programming the cfr1<29:27> bits to logic 101(b), the operation would be identical until the ram segment final address value for profile 2 is reached. at this point, instead of stopping the sequence, it repeats, starting with profile 0.
ad9953 rev. a | page 22 of 32 trol. ter utput signal is offset y a constant angle relative to the nominal signal. this allows put with some external d meth here the user regularly tes the phas port. by properly ifying the ph implement a pha however, both the of the i/o rate at which pha allo f hase accum automatic zeroin olled via th phase mulator bit. holds the value t tinuous cle he continuous clear bit is simply a static control signal that, nt s the -off d. he r value into the amplitude scale factor (asf) register. he shaped on-off keying function may be bypassed (disabled) by clearing the osk enable bit (cfr1<25> = 0). e most signifi- unction register (cfr). cfr1<25> is e tive ode off keying mode operation termined he osk all 0s he dds core output by 16383 (decimal). nally generated scale factor step size <15:14> bits. table 8 describes the e ts of the amplitude he user to ramp to a value less programming ad9953 features phase offset control a 14-bit phase offset () may be added to the output of the phase accumulator by means of the control registers. this feature provides the user with two different methods of phase con the first method is a static phase adjustment where a fixed phase offset is loaded into the appropriate phase offset regis and left unchanged. the result is that the o b the user to phase align the dds out a . signal, if necess the secon ry od of phase control is w upda e offset register via the i/o mod ase offset as a function of time, the user can se modulated output signal. speed port and the frequency of sysclk limit the se modulation can be performed. the ad9953 ws for a programmable continuous zeroing o the p ulator as well as a clear and release or g function. each feature is individually contr e cfr1 bits. cfr1<13> is the automatic clear accu cfr1<10> clears the phase accumulator and o zero. con ar bit t when active high, holds the phase accumulator at zero for the entire time the bit is active. when the bit goes low, inactive, the phase accumulator is allowed to operate. clear and release function when set, the auto-clear phase accumulator clears and releases the phase accumulator upon receiving an i/o update. the automatic clearing function is repeated for every subseque i/o update until the appropriate auto-clear control bit is cleared. shaped on-off keying the shaped on-off keying function of the ad9953 allow user to control the ramp-up and ramp-down time of an on emission from the dac. this function is used in burst transmissions of digital data to reduce the adverse spectral impact of short, abrupt bursts of data. auto and manual shaped on-off keying modes are supporte the auto mode generates a linear scale factor at a rate determined by the amplitude ramp rate (arr) register controlled by an external pin (osk). manual mode allows t user to directly control the output amplitude by writing the scale facto t the modes are controlled by two bits located in th cant byte of the control f the shaped on-off keying enable bit. when cfr1<25> is set, th output scaling function is enabled and cfr1<25> bypasses the function. cfr1<24> is the internal shaped on-off keying ac bit. when cfr1<24> is set, internal shaped on-off keying m is active; cfr1<24> is cleared, external shaped on-off keying mode is active. cfr1<24> is a dont care if the shaped on-off keying enable bit (cfr1<25>) is cleared. the power-up condition is shaped on-off keying disabled (cfr1<25> = 0). figure 20 shows the block diagram of the osk circuitry. auto shaped on- the auto shaped on-off keying mode is active when cfr1<25> and cfr1<24> are set. when auto shaped on-off keying mode is enabled, a single scale factor is internally generated and applied to the multiplier input for scaling the output of the dds core block (see figure 20 ). the scale factor is the output of a 14-bit counter that increments/decrements at a rate de by the contents of the 8-bit output ramp rate register. the scale factor increases if the osk pin is high and decreases if t pin is low. the scale factor is an unsigned value such that multiply the dds core output by 0 (decimal) and 0x3fff multiplies t for those users who use the full amplitude (14 bits) but need fast ramp rates, the inter is controlled via the asf increment/decrement step size of the internally generated scal factor per the asf<15:14> bits. a special feature of this mode is that the maximum output amplitude allowed is limited by the conten scale factor register. this allows t than full scale. table 8. auto-scale factor internal step size asf<15:14> (binary) increment/decrement size 00 1 01 2 10 4 11 8
ad9953 rev. a | page 23 of 32 nt of 1 he first method of loading is by changing the osk input pin. hen the osk input pin changes state, the asfr value is aded into the ramp rate timer, which then proceeds to count own as normal. he second method in which the sweep ramp rate timer can be aded before reaching a count of 1 is if the load osk timer bit fr1<26>) is set and an i/o update is issued. he third method in which the sweep ramp rate timer can be oaded before reaching a count of 1 is when going from the active auto shaped on-off keying mode to the active auto aped on-off keying mode; that is, when the sweep enable bit is eing set. osk pin syn to d le > osk ramp rate timer the osk ramp rate timer is a loadable down counter, which generates the clock signal to the 14-bit counter that generates the internal scale factor. the ramp rate timer is loaded with the value of the asfr every time the counter reaches 1 (decimal). this load and countdown operation continues for as long as the timer is enabled, unless the timer is forced to load before reaching a count of 1. if the load osk timer bit (cfr1<26>) is set, the ramp rate timer is loaded upon an i/o update or upon reaching a value a cou t w lo d t lo (c t l in sh of 1. the ramp timer can be loaded before reaching by three methods. b dds core osk enab cfr<25 amplitude scale factor register (asf) load osk timer cfr1<26> c_clk auto desk enable cfr1<24> ac 0 0 1 03374-0-005 r ramp rate timer clock auto scale ctor generato fa 01 01 hold ec enable inc/d out cos(x) amplitude ramp rate register (asf) up/dn data load en f shaped key figure 20. on-of ing block diagram
ad9953 rev. a | page 24 of 32 external shaped on-off keying mode operation the external shaped on-off keying mode is enabled by writing cfr1<25> to a logic 1 and writing cfr1<24> to a logic 0. when configured for external shaped on-off keying, the content of the asfr becomes the scale factor for the data path. the scale factors are synchronized to sync_clk via the i/o update functionality. synchronization; register updates (i/o update) functionality of the sync_clk and i/o update data into the ad9953 is synchronous to the sync_clk signal (supplied externally to the user on the sync_clk pin). the i/o update pin is sampled on the rising edge of the sync_clk. internally, sysclk is fed to a divide-by-4 freque roduce the sync_clk signal. the sync_clk signal is rovided to the user on the sync_clk pin. this enables ynchronization of external hardware with the devices internal ocks. this is accomplished by forcing any external hardware obtain its timing from sync_clk. the i/o update signal coupled with sync_clk is used to transfer internal buffer contents into the control registers of the device. the combina- tion of the sync_clk and i/o update pins provides the user with constant latency relative to sysclk, and also ensures phase continuity of the analog output signal when a new tuning word or phase offset value is asserted. figure 21 demonstrates an i/o update timing cycle and synchronization. notes for synchronization logic: 1. the i/o update signal is edge detected to generate a single rising edge clock signal that drives the register bank flops. the i/o update signal has no constraints on duty cycle. the minimum low time on i/o update is one sync_clk clock cycle. 2. the i/o update pin is set up and held around the rising c_clk and has zero hold time and 4 ns setup time. sysclk sync_clk disable ncy divider to edge of syn p p s cl to 03374-0-006 sdi 0 10 4 osk profile<1:0> i/o update sclk to core logic cs d q d q d q sync_clk gating edge detection logic register memory i/o buffer latches figure 21. i/o synchronization block diagram
ad9953 rev. a | page 25 of 32 sysclk sync_clk i/o update ab data in i/o buffers data 1 da data in re gisters data 0 the device registers an i/o update at point a. figure ab ta 2 data 3 data the data is trans 22. i/o synchronization tim ser: ons must be observed. first, all units must share a common clock source. trace lengths and path impedance of the clock tree must be designed to keep the phase delay of the different clock branches as closely matched as possible. second, the i/o update signals rising edge must be provided synchronously to all devices in the system. finally, regardless of the internal synchronization method used, the dvdd_i/o supply should be set to 3.3 v for all devices that are to be synchronized. avdd and dvdd should be left at 1.8 v. in automatic synchronization mode, one device is chosen as a master; the other device(s) will be slaved to this master. when configured in this mode, the slaves will automatically synchron- ize their internal clocks to the sync_clk output signal of the master device. to enter automatic synchronization mode, set the slave devices automatic synchronization bit (cfr1<23> = 1). connect the sync_in input(s) to the master sync_clk output. the slave device will continuously update the phase relationship of its sync_clk until it is in phase with the sync_in input, which is the sync_clk of the master device. when attempting to synchronize devices running at sysclk speeds beyond 250 msps, the high speed sync enhancement enable bit should be set (cfr2<11> = 1). n software manual synchronization mode, the user forces the evice to advance the sync_clk rising edge one sysclk ycle (1/4 sync_clk period). to activate the manual nchronization mode, set the slave devices software manual ynchronization bit (cfr1<22> = 1). the bit (cfr1<22>) will be eared immediately. to advance the rising edge of the sync_clk ultiple times, this bit will need to be set multiple times. in h inpu configured such that it will now advance the rising dge of the sync_clk signal each time the device detects a sing edge on the sync_in pin. to put the device into hard- are manual synchronization mode, set the hardware manual synchronization bit (cfr2<10> = 1). unlike the software manual synchronization bit, this bit does not self clear. once the hardware manual synchronization mode is enabled, all rising edges detected on the sync_in input will cause the device to advance the rising edge of the sync_clk by one sysclk cycle until this enable bit is cleared (cfr2<10> = 0). using a single crystal to drive multiple ad9953 clock inputs the ad9953 crystal oscillator output signal is available on the crystal out pin, enabling one crystal to drive multiple ad9953s. in order to drive multiple ad9953s with one crystal, the crystal out pin of the ad9953 using the external crystal should be connected to the refclk input of the other ad9953. the crystal out pin is static until the cfr2<9> bit is set, enabling the output. the drive strength of the crystal out pin is typically very low, so this signal should be buffered prior to using it to drive any loads. serial port operation with the ad9953, the instruction byte specifies read/write operation and the register address. serial operations on the ad9953 occur only at the register level, not the byte level. for e serial po t controller recognizes the instruc- tion byte register address and automatically generates the proper register byte address. in addition, the controller expects that all bytes of that register will be accessed. it is required that all bytes of a register be accessed during serial i/o operations, with one exception. the iosync function can be used to abort an i/o operation, thereby allowing some, but not all bytes to be accessed. 1 data 2 ferred from the i/o buffers at point b. 03357-007 ing diagram synchronizing multiple ad9953s the ad9953 allows easy synchronization of multiple ad9953s. there are three modes of synchronization available to the u an automatic synchronization mode, a software controlled manual synchronization mode, and a hardware controlled manual synchronization mode. in all cases, when a user wants to synchronize two or more devices, the following considera- ti i d c sy s cl m ardware manual synchronization mode, the sync_in t pin is e ri w the ad9953, th r
ad9953 rev. a | page 26 of 32 there are two phases to a communication cycle with the ad9953. phase 1 is the instruction cycle, which is the writing of an instruction byte into the ad9953, coincident with the first eight sclk rising edges. the instruction byte provides the ad9953 serial port controller with information regarding the data transfer cycle, which is phase 2 of the communication cycle. the phase 1 instruction byte defines whether the upcoming data transfer is read or write and the serial address of the register being accessed. the first eight sclk rising edges of each communication cycle are used to write the instruction byte into the ad9953. the remaining sclk edges are for phase 2 of the communication cycle. phase 2 is the actual data transfer between f bytes transferred during phase 2 of the communication cycle is a function of the register being accessed. for example, when accessing the control function register no. 2, which is three bytes wide, phase 2 requires that three bytes be transferred. if accessing the frequency tuning word, which is four bytes wide, phase 2 requires that four bytes be transferred. after transferring all data bytes per the instruction, the communication cycle is completed. at the completion of any communication cycle, the ad9953 serial port controller expects the next eight rising sclk edges to be the instruction byte of the next communication cycle. all data input to the ad9953 is registered on the rising edge of sclk. all data is driven out of the ad9953 on the falling ge 23 through figure 26 are useful in voefstuboe ing the general operation of the ad9953 serial port. th e ad9953 of sclk. figure and the system controller. the number o ed 03374-0-008 i 6 i 5 i 4 i 3 i 2 i 7 instruction cycle i 1 i 0 d d 5 d 4 d 3 d 2 d 1 d 0 7 d 6 sclk sdio data transfer cycle cs ngclock stall low figure 23. serial port write timi 03374-0-009 i 6 i 5 i 4 i 3 i i 7 instruction cycle data transfer cycle 2 i 1 i 0 don't care sclk sdio d d o 5 d o 4 d o 3 d o 2 d o 1 d o 0 o 7 d o 6 sdo cs imingclock stall low figure 24. 3-wire serial port read t 03374-0-010 i 6 i 5 i 4 i 3 i 2 i 7 instruction cycle i 1 d 0 i 0 d d d d d d d 5 4 3 2 1 7 6 sclk sdio data transfer cycle cs write timi figure 25. serial port ngclock stall high 03374-0-011 i 6 i 5 i 4 i 3 i i 7 2 i 1 i 0 d o 5 d o 4 d o 3 d o 2 d o 1 d o 0 d o 7 d o 6 instruction cycle sclk sdio data transfer cycle cs mingclock stall high figure 26. 2-wire seri al port read ti
ad9953 rev. a | page 27 of 32 d3 instruction byte the instruction byte contains the following information: table 9. msb d6 d5 d4 d2 d1 lsb r/ w a3 x x a4 a2 a1 a0 r/ w bit 7 of th e instruction byte determines whether a read etermine which register is accessed during the data transfer portion of the communications cycle. serial interface port pin description sclkserial clock. the serial clock pin is used to synchronize data to and from the ad9953 and to run the internal state machines. sclk maximum frequency is 25 mhz. csbchip select bar. csb is active low input t an one device on the same serial communications line. the sdo and sdio pins will go to a high impedance state when this input is high. if driven high during any communications cycle, that cycle is suspended until cs or write data transfer will occur after the instruction byte write. logic high indicates read operation. logic 0 indicates a write operation. x, xbits 6 and 5 of the instruction byte are dont care. a4, a3, a2, a1, a0bits 4, 3, 2, 1, 0 of the instruction byte d hat allows more th is reactivated low. chip select can be tied low in systems that maintain control of sclk. sdioserial data i/o. data is always written into the ad9953 on this pin. however, this pin can be used as a bidirectional data line. bit 9 of register address 0x00 controls the configuration of this pin. the default is logi nfigures the sdio pin as bidirectional. sdoserial data out. data is read from this pin for protocols that use separate lines for transmitting and receiving data. in the case where the ad9953 operates in a single bidirectional i/o mode, this pin does not output data and is set to a high impedance state. iosyncit synchronizes the i/o port state machines without affecting the addressable registers contents. an put on the iosync pin causes the current communication ycle to abort. after iosync returns low (logic 0), another communication cycle may begin, starting with the instruction byte write. msb/lsb transfers the ad9953 serial port can support both most significant bit (msb) first or least significant bit (lsb) firs unctionality is controlled by the control register 0x00 <8> bit. he default value of control register 0x00 <8> is low (msb rst). when control register 0x00 <8> is set high, the ad9953 rial port is in lsb first format. the instruction byte must be ddress first i/o operation is complete. all data written to (read from) the ad9953 must be (will be) in msb first order. if the lsb mode is active, the serial port controller will generate the least signifi- cant byte address first followed by the next greater significant byte addresses until the i/o operation is complete. all data written to (read from) the ad9953 must be (will be) in lsb first order. example operation tude scale factor register in msb first format, apply an instruction byte of 0x02 [serial address is 00010(b)]. from this instruction, the internal controller will know to use the first byte as the most significant byte. the first two bits will be recorded as the auto ramp rate speed control bits, and the next six bits will be the most significant bits of the amplitude scale factor. the second byte will be applied as the eight less significant bits of the amplitude scale factor asf<7:0>. to write the amplitude scale factor regis sb first format, l register has already been set for lsb first format, apply an instruction byte of 0x40. from this instruction, the internal controller will know to use the first byte as the least significant byte of the amplitude scale factor asf<0:7>. the second byte will be split into the first six bits asf<8:13> and the last two will provide the auto ramp rate speed control bits arrsc<0:1>. d9953 the ad9953 supports an externally controlled or hardware power-down feature as well as the more common software programmable power-down bits found in previous adi dds products. the software control power-down allows the dac, pll, input clock circuitry, and digital logic to be individually powered down via unique control bits (cfr1<7:4>). with the exception ts are not active when the externally controlled power-down pin (pwrdwnctl) is high. external power-down control is supported on the ad9953 via the pwrdwnctl input pin. when the pwrdwnctl input pin is high, the ad9953 will enter a power-down mode based on the cfr1<3> bit. when the pwrdwnctl input pin is low, the external power-down control is inactive. c 0, which assuming the contro co active high power-down functions of the a in c t data formats. this of cfr1<6>, these bi f t fi se written in the format indicated by control register 0x00 <8>. if the ad9953 is in lsb first mode, the instruction byte must be written from least significant bit to most significant bit. for msb first operation, the serial port controller will generate the most significant byte (of the specified register) a followed by the next lesser significant byte addresses until the to write the ampli ter in l
ad9953 rev. a | page 28 of 32 when the cfr1<3> bit is 0 and the pwrdwnctl input pin is high, the ad9953 is put into a fast recovery power-down mode. in this mode, the digital logic and the dac digital logic are powered down. the dac bias circuitry, pll, oscillator, and clock input circuitry is not powered down. when the cfr1<3> bit is high, and the pwrdwnctl input pin is high, the ad9953 is put into the full power-down mode. in this mode, all functions are powered down. this includes the dac and pll, which take a significant amount of time to power up. when the pwrdwnctl input pin is high, the individual power-down bits (cfr1<7>, <5:4>) are invalid (dont care) and unused. when the pwrdwnctl input pin is low, the individual power-down bits control the power-down modes of operation. note that the power-down signals are all designed such that a logic 1 indicates the low power mode and a logic 0 indicates the active or power-up mode. table 10 indicates the logic level for each power-down bit that drives out of the ad9953 core logic to the analog section and the digital clock generation section of the chip for the external power-down operation. layout considerations for the best performance, the following layout guidelines should be observed. always provide the analog power supply (avdd) and the digital power supply (dvdd) on separate supplies, even if just from two different voltage regulators driven by a common supply. likewise, the ground connections (agnd, dgnd) should be kept separate as far back to the source as possible (i.e., separate the ground planes on a localized board even if the grounds connect to a common point in the system). bypass capacitors should be placed as close to the device pin as possible. usually a multitiered bypassing scheme consisting of a small high frequency capacitor (100 pf) placed close to the supply pin and progressively larger capaci- tors (0.1 f, 10 f) placed further away from the actual supply source works best. table 10. power-down control functions control mode active description pwrdwnctl = 0 cfr1<3> dont care software control digital power-down = cfr1<7> dac power-down = cfr1<5> input clock power-down = cfr1<4> pwrdwnctl = 1 cfr1<3> = 0 external control, fast recovery power-down mode digital power-down = 1b1 dac power-down = 1b0 input clock power-down = 1b0 pwrdwnctl = 1 cfr1<3> = 1 external control, full power-down mode digital power-down = 1b1 dac power-down = 1b1 input clock power-down = 1b1
ad9953 rev. a | page 29 of 32 suggested application circuits 03357-0-003 lpf ad9953 refcl k rf/if input modulated/ demodulated signal 03357-0-004 figure 27. synchronized lo for up conversion/down conversion filter phase comparator loop filter ad9953 tuning world ref signal vco figure 28. digitally programmable divide-by-n function in pll 03357-006 tuning crystal frequency word phase word 2 baseband frequen c y offset i/i-bar tuning word p hase et d 1 offs wor q/q-bar baseband sync in ad9953 dds refclk refclk refclk lpf sync out crystal out ad9953 dds iout iout lpf iout iout rf o ut ith independent phase offsets for nulling figure 29. two ad9953s synchronized to provide i and q carriers w
ad9953 rev. a | page 30 of 32 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. compliant to jedec standards ms-026-abc outline dimensions 0.50 bsc lead pitch 9.00 bsc sq 0.27 0.22 0.17 7.00 bsc sq 37 37 48 48 1 13 1 12 24 13 24 25 36 25 36 12 1.05 1.00 0.20 0.09 0.95 0.08 max coplanarity view a rotated 90 ccw seating plane 0 min 7 3.5 0 0.15 0.05 0.75 0.60 0.45 1.20 max view a top view (pins down) bottom view (pins up) pin 1 3.50 sq exposed pad 011708-a figure 30. 48-lead thin quad flat package, exposed pad [tqfp_ep] (sv-48-4) dimensions shown in millimeters rdering guide odel temperature range package description ordering quantity package option o m ad9953y sv ?40c to +105c 48-lead thin quad flat package, exposed pad [tqfp_ep] sv-48-4 a d9953ysv-reel7 ?40c to +105c 48-lead thin quad flat package, exposed pad [tqfp_ep] 500 sv-48-4 a d9953ysvz 1 ?40c to +105c 48-lead thin quad flat package, exposed pad [tqfp_ep] sv-48-4 AD9953YSVz-reel7 1 ?40c to +105c 48-lead thin quad flat package, exposed pad [tqfp_ep] 500 sv-48-4 ad9954/pcbz 1 evaluation board used for the ad9953 1 z = rohs compliant part.
ad9953 rev. a | page 31 of 32 notes
ad9953 rev. a | page 32 of 32 ?2004C2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d03374-0-5/09(a) notes

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